These three things are the same story: Amazon's custom AI silicon, a grid of compute units, and the problem of keeping that grid busy. US11868895B2 (granted January 9, 2024, to Amazon Technologies) describes dynamically expanding the processing-element array, the chip's compute fabric, to match what a given workload needs.
Connect the dots to why this is clever. AI accelerators are built around a systolic array: a grid of tiny units that pass data to their neighbors while multiplying. Different layers of a neural network want different grid shapes, a wide layer wants a wide array, a deep one wants depth. A fixed grid wastes units on mismatched layers. Dynamic expansion reshapes the effective array to fit.
Follow both the money and the IP. Amazon designs its own training and inference chips (Trainium, Inferentia) precisely to control cost in its cloud. A patent on making the compute fabric adapt to the workload is a patent on utilization, squeezing more useful work out of each transistor it pays to fabricate and power.
This rhymes with everything else in the AI-silicon story we've traced: dataflow, scheduling, batching, hierarchy. The unifying theme is that raw compute is necessary but not sufficient; the wins come from keeping that compute fed and matched to the work. Amazon's reconfigurable array is the hardware expression of that obsession.
House caveat: it's a granted patent, so the claims set the real scope, and dynamic expansion is an architecture, not a quoted speedup. As a dated marker it's strong, by the start of 2024, a hyperscaler with its own chips was patenting silicon that reshapes its compute grid on the fly to chase utilization.