Almost every neural network you have heard of is, physically, a digital program. The weights are numbers in memory, the multiply-accumulate operations run on a GPU or accelerator, and training happens by backpropagation: compute the output, compute the error, and push that error backward through the network to work out how much each weight should change. It is enormously effective and enormously expensive, and the expense is increasingly the story — the energy, the memory bandwidth, the round trips between storage and arithmetic units. A patent application published in this week's drop takes the opposite tack. Instead of representing the network as numbers a processor crunches, it builds the network as an actual analog electrical circuit and lets the circuit's own physics carry part of the learning.

The hero record is US20260178874A1, "Analog Neural Network," published June 25, 2026 as a pending US application. The disclosed network is a stack of layers wired together into a single circuit with an input and an output. The input takes an electrical signal corresponding to an example; the output is the network's electrical response. Inside each layer are four kinds of element connected together: at least one programmable electronic element that physically represents a weight of the network, at least one non-linear element (the analog stand-in for an activation function), at least one amplifier block, and an "error element." Each layer also carries measurement elements that watch what is happening across the error element and at the input to the weight element. The whole thing is an electrical circuit whose steady-state behavior is the forward pass.

An analog neural network is described comprising: a plurality of layers connected to form an electrical circuit having an input and an output, the input suitable for receiving an electrical signal corresponding to an input example and the output corresponding to an output of the neural network. Each layer comprises elements connected together, where the elements comprise: at least one programmable electronic element representing a weight of the neural network; at least one non-linear element; at least one amplifier block; an error element. Each layer also comprises a measurement element for measuring a change in an electrical signal across the error element.— Analog Neural Network, US20260178874A1

How the circuit learns without backpropagation

The interesting part is the training procedure, because it sidesteps the thing that makes backpropagation costly: explicitly propagating an error signal backward through every layer. Forget the name for a second and follow the mechanism. To train, the application describes clamping the input to the electrical signal for a training example and, at the same time, clamping the output to an electrical value that represents the ground-truth label. With both ends pinned, the circuit is left to settle into a steady state — an equilibrium the physics finds on its own. Once it has settled, two local measurements are taken at each element: an electrical signal V across the error element, and the weight input U at the programmable element. A "measurement and update element" then reads those two values and updates the weight.

What makes this work conceptually is a second pass that the dependent claims spell out. The circuit is also allowed to settle with only the input clamped — the output left free — and the error signal is measured again in that state. The weight change the application describes is, in its own words, "approximately equal to the negative difference between the error V observed when the analog neural network is at equilibrium with both the first clamp and the second clamp in place, and the error Error_f observed when the analog neural network is at equilibrium with only the first clamp in place, times the weight input U." In plain terms: nudge the network toward the right answer by clamping the output, see how its internal voltages differ from when the output was free, and use that local difference — available right at each weight, no backward sweep required — as the learning signal. This is the family of ideas the research community calls equilibrium- or contrast-based learning, and the application's contribution is a concrete circuit for it, with programmable weight elements, amplifiers, non-linear elements, and an error element per layer that make the two measurements physically readable.

One pragmatic detail in the filing is worth flagging because it tells you where the engineering tension lives. The disclosure offers both an all-analog update (apply the measured signal back to the programmable element as analog voltage pulses) and a hybrid path where, per independent claim 1, "the measurement and update element is digital and uses a digital process to compute updates of weights" and stores them in memory before applying them. That hybrid is the realistic compromise: let the circuit do the expensive physics — the forward relaxation and the local measurements — but compute and bookkeep the weight updates digitally, where precision and control are easier. It is the same instinct you see across the rest of this week's machine-learning hardware filings.

Where it sits in this week's drop, and in the field

For context on the drop itself: machine learning (CPC class G06N) was the single largest category in this week's published-application batch, with on the order of 97 G06N applications — the kind of volume that makes the category a fair barometer of where AI engineering effort is pointed right now. A striking share of the hardware-flavored entries cluster around exactly the idea behind the hero record: doing the arithmetic of a neural network in the analog domain, close to or inside memory, rather than shuttling numbers to a digital arithmetic unit. Read together they sketch the same state-of-the-art frontier from several angles.

The most direct neighbor is US20260180593A1, "Multiply-Accumulate (MAC) Apparatus for In-Memory Computing," which describes a capacitive charge-coupling analog compute-in-memory bitcell array that produces an analog output voltage for a multiply-accumulate result and feeds it into an activation module switchable between deep-neural-network and spiking-neural-network modes. Multiply-accumulate is the single operation a neural network does billions of times; doing it as charge on capacitors inside the memory array is the canonical analog-AI move. Alongside it, US20260181942A1 describes processing input variables with field-effect transistors so that a transistor's threshold voltage and gate control jointly compute a product — multiplication realized in device physics, aimed explicitly at compute-in-memory and artificial neural networks. And US20260178697A1, classified under G06N 3/045 and G06N 3/06, describes a method for computing a matrix product on an in-memory-computing hardware unit whose cells store one matrix and accumulate partial products in parallel — the matrix-multiply backbone of a neural layer, again pushed into the memory fabric.

The device-physics layer of the same trend shows up too. US20260181911A1, classified under G06N 3/065, describes a neuron device based on a magnetic tunnel junction and a neural-network apparatus built from it — using the magnetic state of a junction as a synaptic or neuronal element. US20260181907A1 describes a back-end-of-line-compatible ferroelectric capacitive synaptic device that switches between high- and low-capacitance states by flipping ferroelectric dipoles, explicitly framed for multi-tier 3D stacking in in-memory computing. Different materials, same destination: a physical element whose tunable state stores a weight and participates directly in the computation, rather than a number fetched from DRAM.

Place the hero record against that backdrop and its angle becomes clear. The compute-in-memory and synaptic-device filings are mostly about making the forward pass — inference, the multiply-accumulate — cheap in analog hardware. US20260178874A1 reaches further, into training: it proposes a circuit in which learning itself is an equilibrium the hardware settles into, with the update signal read locally off an error element instead of computed by a backward pass. That is the harder and less-solved half of the analog-AI problem, which is what makes it a worthwhile read.

The standard caveat is also the load-bearing one. US20260178874A1 is a published application, not a granted patent, and a published application is a description of an invention, not a benchmarked chip. It tells us how the disclosed approach is meant to work and where it sits relative to the rest of the field's analog-AI effort; it does not tell us how well it trains, at what scale, or which claims will ultimately issue. For a technology reader that is the right altitude anyway. Strip the names and the interesting fact is the mechanism: a neural network rendered as a circuit that learns by being pinned at both ends, allowed to relax, and read locally — a genuinely different answer to the question of where the cost of training a neural network should live.