Here's the surprising connection: as AI chips get more compute units, the hard part stops being can it do the math and becomes can we keep every unit busy. US20220382592A1 (published December 1, 2022) answers by putting the scheduler itself into hardware, a circuit dedicated to traffic-copping the workload.
Connect the dots. Normally a software scheduler decides how to split work across a chip's cores. But software scheduling has overhead, and on a massively parallel accelerator that overhead can become the bottleneck. Moving the decision into a hardware circuit makes it faster and tighter, the chip orchestrates itself at silicon speed.
The CPC pairing tells the story: G06F 9/5027 and 9/4881 are resource-allocation and scheduling classes; G06N 3/063 is neural-network hardware. This is a scheduling patent that lives inside an AI accelerator, exactly the seam where utilization is won or lost.
Why feature it: this is the same insight as the dataflow and batching pieces we've covered, pushed one level deeper into hardware. The recurring lesson of the AI-silicon story is that performance is increasingly about orchestration, keeping expensive compute fed, and the industry is willing to spend transistors on the scheduler itself to get there.
House caveat: a publication describes a circuit design, not a shipping product, and scheduling gains depend entirely on workload. But as a dated marker it's sharp, by the end of 2022, the orchestration of AI work was considered worth dedicating silicon to, not just software.